The case is a (3-1/4" x 2-1/8" x 1-1/8"hi) plastic box from Radio Shack. A new front panel was fabricated from .062 thick transparent red plexiglass to replace the stock aluminum front panel. This was friction fit into the case.
The circuitry is built on a small piece of perfboard with wire wrap sockets that providentially support the readouts flush with the front panel. The readouts are installed in two immediately adjacent 28 pin IC sockets. The center readout straddles the sockets with four pins in each.
The input is a single BNC (SMA on the 6 GHz version) connector on the side of the case. The unit is powered by an external 6VDC wall wart via a 2.1 mm power connector on the side of the case. The prescalers are mounted on a small piece of PCB material mounted under the area of the board where the voltage regulator is seen.
The schematic shown is for the 6 GHz version. The HP IFD-50310 is a 6 GHz capable divide by 4, and the 12079 is configured for divide by 256 for an overall divide by 1024.
I also built a 1 GHz version with a single Toshiba TD6110P (UHF TV) divide by 64 prescaler IC about 10 years ago but, I don't believe that this part is still manufactured. The 12079, which may also be configured to divide by 64, rapidly loses sensitivity below 500 MHz input so, is it not recommended as a replacement.
The 50 MHz version is similar with the deletetion of the two prescaler ICs and their associated circuitry. The value of the input cap to the AC132 is increased to .1uF.
A Microchip PIC 16C54 directly counts the input frequency in BCD and loads the readouts at the end of the gate time. The 74ACT132 schmidt trigger gate conditions the input signal and also provides gating for the external prescaler flush clock.
The 4th section of the gate is shown driving some optional switches which I have never implemented.